Traditional silicon-on-insulator (SOI) integrated circuits are formed on SOI substrates. A cross-section of a silicon-on-insulator (SOI) substrate 10 is illustrated in FIG. 1a. SOI substrates typically have a thin layer of silicon 12, also known as the silicon active layer, disposed on an insulator layer 14 such as the buried oxide (BOX) layer. The insulator layer or the buried oxide layer 14 is provided on a silicon substrate 16. The buried oxide layer 14 is comprised of an insulator such as silicon oxide. It electrically isolates the silicon active layer 12 from the silicon substrate 16.
In a conventional SOI chip, as shown in FIG. 1b, the SOI substrate 10 is processed to form a plurality of active regions 18 in the active layer 12. Active devices 20 such as transistors and diodes may be formed in the active regions 18. Active regions 18 are electrically isolated from each other by isolation regions 22. The size and placement of the active regions 18 are defined by isolation regions 22. Isolation regions 22 may, for example, be formed of shallow trench isolation (STI). Moreover, the active devices 20 are isolated from the substrate 16 by the buried oxide layer 14.
State of the art shallow trench isolation structures typically have a groove-like recess 32 at the isolation edge, as shown in FIG. 1b. This groove-like recess 32 results from commonly used wet-etch processes and the recess is in the range of tens to a two hundred angstroms below the surface of the active layer. When the thickness of the active layer is about one hundred angstroms, the groove-like recess potentially encroaches into the buried oxide and therefore renders the STI ineffective in protecting the buried oxide from being etched during wet cleaning processes. Moreover, the top surface of the isolation may also be recessed. In cases where the shallow trench isolation is exposed to an excessive amount of wet-etch processes, the STI may be entirely etched, resulting in an exposed buried oxide between active regions.
Active devices formed on SOI substrates offer many advantages over their bulk counterparts, including absence of reverse body effect, absence of latch-up, soft-error immunity, and elimination of junction capacitance typically encountered in bulk silicon devices. SOI technology therefore enables higher speed performance, higher packing density, and reduced power consumption. At present, commercial products using SOI technology employ an uniform active layer thickness and shallow trench isolation.
One type of SOI transistor employs a very thin silicon active layer. For example, the silicon active layer thickness can be as thin as a third of the gate length. If the gate length is 30 nm, the silicon active layer may have a thickness of 10 nm or thinner. This type of SOI transistor is known as ultra-thin body (UTB) transistors or depleted-substrate transistors (DSTs).
When the thickness of the silicon active layer is as thin as 10 nm, mesa isolation could be a more appropriate isolation scheme for the transistors as compared to shallow trench isolation. In mesa isolation, trenches 24 are formed in the active layer 12, as shown in FIG. 2a. The trenches 24 extend from the surface of the active layer 12 to the buried oxide layer 14. These trenches divide the active layer into silicon islands or silicon mesa structures 26. The mesa isolation method thus cuts electrical connection between adjacent active regions by removing portions of the active layer in the SOI substrate.
One major problem of the mesa isolation is that the exposed buried oxide layer surface 28 will be recessed in subsequent chemical treatments such as wafer cleaning steps. This issue is illustrated in FIG. 2b. The recessed buried oxide results in a number of problems. For example, it leads to an increased parasitic capacitance between the substrate and metal lines running over the buried oxide. It also leads to a concentration of electric field lines around the exposed corners 30 of the silicon mesas 26, which potentially impact device reliability.
In U.S. Pat. No. 5,904,539 issued to Hause et al., a trench isolation process is described for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. This approach is similar to shallow trench isolation.
In U.S. Pat. No. 6,410,938 issued to Xiang, semiconductor-on-insulator devices isolated by a nitrided buried oxide are described for the reduction of dopant penetration from the active layer into the buried oxide. The nitrided buried oxide is formed by an implantation of nitrogen or nitrogen-containing species through the semiconductor active layer to reach the buried silicon oxide.
In U.S. Pat. No. 5,468,657 issued to Hsu, a method is provided for improving the electrical isolation in SIMOX buried oxide wafers. In that invention, nitrogen ions are implanted into a wafer to approximately the same depth as oxygen ions are implanted during SIMOX processing. A subsequent heating step causes the nitrogen ions to migrate to the interface region between the buried oxide and the upper and lower semiconductor regions of the substrate. The nitrogen passivates the interface region to reduce the presence of buried free electrons trapped in the substrate.